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Altera_Forum
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7 years ago

How to design ALM for Aria 10?

I have two simple 5-input and 3-input functions in Verilog. Function 1: 3:1 Multiplexer input a,b,c; input [1:0] s1; output wire east; Function 2 : 2:1 Multiplexer input d,e; ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

Hi,

Thanks for the help. There was a (*KEEP*) attribute in my multiplexer code which was leading to generating 2 ALMs. As I removed the attribute, the compiler is using 1 ALM.