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Altera_Forum
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7 years ago

How to design ALM for Aria 10?

I have two simple 5-input and 3-input functions in Verilog. Function 1: 3:1 Multiplexer input a,b,c; input [1:0] s1; output wire east; Function 2 : 2:1 Multiplexer input d,e; ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
7 years ago

What is your goal here? Are you concerned about resource usage? Yes, the compiler should be able to do what you are referring to. Are you looking at the Fitter compilation report or just synthesis? If it's just synthesis, it's not optimized yet for actual resource use.