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Honored Contributor
Honored ContributorHow to define 2-port RAM output (old data or don't care)
Hello, does anyone know how to define 2-port RAM output(q) for read-during-write? I am using simple 2-port RAM(1 port with read and write) with separate read and write clock(wr_clk, rd_clk) and I...
Altera_ForumHonored Contributor
Honored ContributorHi konyemko,
the "Read-During-Write" only makes sense when using the same clocks for read and write. When using separate clocks for both sides, you can not assume a relationship between the two clocks and therefore you can not select the "Read-During-Write" option in this case. Hope this helps...
