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Altera_Forum's avatar
Altera_Forum
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16 years ago

how to "cut" a vector...

hi guys, i have small question.

you see i got this project and i need to build this unit , which receives "packages" in serial communication mode (also i need to know how to do it for parallel communication mode ,for the final exam). the package structure is like that : first 3 bits are address, next 3 bits are number of "data" received , and the last 8 bits are the "data".

now everything comes in one "package" . the question is how can i divide the vector into : 3,3, 8 ? and save only the last 8 bits into a fifo component ?

thanks in advance

.

9 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    You don't tell your what's your HDL entry method. Each language has simple constructs to access array slices, it's also easy in schematic entry.

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    The number of bits doesn't fit your example...

    The last 8 bit's can be accessed like

    data <= allvector(7 to 14);

    The expression is called an array slice in VHDL terminology.
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    wait let me understand , if i got : data_in : in std_logic_vector( 7 downto 0) and i want to slice it to 5, and 3 : so i need to write : data1<=allvector(7 downto 3) and data2<=allvector( 2 downto 0 ) ?

  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    Yes, the bit order of your input vector may be different, however. With numeric data, a descending data direction is usual, as you wrote above for data_in. It's more clear, if you use the same direction for all involved signals, e.g. all_vector(13 downto 0). Serial data streams that are shifted in can still be LSB or MSB first, so it's best to specify clearly the bit allocation of each sub vectors. I would expect this as a standard: 

    address <= all_vector(13 downto 11);
datanum <= all_vector(10 downto 8);
data <= all_vector(7 downto 0);
  • Altera_Forum's avatar
    Altera_Forum
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    16 years ago

    thanks guys , and the last question how do i add them all after i finish doing some operations on them , do i use the "&" sign or the "+" sign ?

    like :

    data :out std_logic_vector ( 13 downto 0 );

    data<= address (13 downto 11) & datanum (10 downto 8) & (7 downto 0);