How to constraint my design using TimeQuest?

So I have some updates:

I think that the SO/MISO waveform is arriving a bit late. The difference between the falling edge of SO and the rising edge of SCK (where the MCU samples) is just 40 ns. I'm thinking that, occasionally, the waveform arrives too late and I get a bad transfer. The AVR datasheet states 10 ns for setup and hold but these are typical values. Min/max are not provided.

Here's a o-scope picture with SCK at 2 Mhz. The top waveform is MISO and bottom is SCK.

http://i.imgur.com/EQWzz.png

Same waveforms at higher timebase:

http://i.imgur.com/jUpqx.png

and here's another picture with SCK at 1 MHz:

http://i.imgur.com/ewmQj.png

At 1 Mhz, the waveform arrives in time very comfortably but I think 2 MHz is a bit of an edge case. I'd prefer to make it arrive a bit earlier. I adjusted the SDC constraints but they had little effect. I'm beginning to think that it might be because of my design.

The other thing I noticed is that my SCK's frequency doesn't stay constant - it increases to 2.1 Mhz and decreases some too. My guess is that because the MCU is running from it's internal RC oscillator. It could be that, once in a while, SCK's freq. increases just slightly and because of the very narrow time to setup MISO, it reads in a bad value?

Tomorrow, I will calibrate the internal RC oscillator and see if SCK's performance improves. However, any suggestions on what to do with my CPLD design? Will I need to increase the sys_clk frequency if I want SCK t obe 2 MHz? A lot of designs can run at just 1/4th the system frequency but I'm having to run at less than 1/10th! Would appreciate any advice on where to go from here.