How to constraint my design using TimeQuest?

That's a good test: change the speed of sys_clk vs SCK.

This way, you can pin-point which interface is giving you problems: the PO/PI or the SPI interface.

Also, if the situation improves when you lower the operating frequency, there are two main possibilities.

One, you have a setup timing problem. That means, some signal is taking too much time to become stable and, occasionally, it's samples before it has becomes stable.

But again, with a 7 ns rise time I don't see that happening.

Another possibility is Inter Symbol Interference: the signal of one bit overlaps with another one and as a result U2 samples the wrong value. You can try to take a look at the eye

pattern of PI.

Try to see if the error is specific to a given signal in the PI vector or if it's random.

But you can pretty much discard hold violation issues.

A third possibility: the problem is noise related and it's also happening at 1 MHz, you just haven't noticed it yet.