Honored Contributor
Honored ContributorWith a 8 MHz MCU, I guess the time between CS_U1 going down up and CS_U2 going will probably be several times 125 ns. So, plenty of time to meet setup time.
And since you're not changing the values right after U2 samples them, plenty of time to meet hold time. Really, don't see why it's failing occasionally. That said.. - U2 samples PI at the rising edge of clk.. when CS_sync is '1', not CS. So, it's happening 2 clocks later. You probably have something similar in U1, so it evens out. But best keep it in mind. - The signal can take some time from U1 setting it and becoming stable at U2's inputs, because of the pull-up scheme, connection cable, etc. I've seen pull-up schemes being unexpectedly slow, so this would be my first guess. - Since there are two different boards, the clocks at U1 and U2 won't be in perfect phase and this may work against you too. Try to draw a timing diagram of the signals involved, it's usually worth the trouble. Try measuring the delay between the rising edge of U2's clock and PI[*] reaching a stable value. Try to get a min/max range for some of the 72 signals. This will be the min/max input delays you should to set on PI, by the way. Other nice things to measure may be the phase between U1's clock and U2's clock; and the time between U1's CS and U2's CS.
