Honored Contributor
Honored ContributorThe resistors are 100 Ohms and the rising edges, after slowing down, are about 7 ns. So I don't think the signal is that slow.
As I mentioned, the other CPLD/FPGA (let's call this U1) n the design, has 72 outputs which connect to the 72 inputs of this CPLD (U2). We connect them together via a group of wires (these are actually the things the board tests by driving a test vector onto them). The U1 CPLD doesn't connect directly but instead drives 72 MOSFETs which in turn buffer the signals on the bunch of wires. To reduce ringing, I have a 1 K resistor at the gate and a 1 K pull-up as well (again, due to my inexperience, I didn't realize that I could control the ringing better via clamping diodes. A termination resistor wouldn't work well because the wires are not good transmission lines and their Zo varies. The next revision of the board will have clamping diodes instead of 1 K resistors to slow down the signal). The pull-up is located near to U2 so that it has a default value incase the wires are not connected. It could be that the 1K resistor + the length of the wire is causing the signal to appear a bit too late? However, I do sample PI at every rising edge of sys_clk, so I'm not sure. Will I need to increase the input delay for PI?
