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Altera_Forum
Honored Contributor
Honored ContributorHow to constraint my design using TimeQuest?
I am looking for some help to constrain my design. I've never done a timing constraint and my understanding of the subject isn't very deep at all. An overview of my design: it consists of a 72 ...
Altera_ForumHonored Contributor
Honored ContributorRandom thoughts
a) I'd say there's no problem with SO. Even if you wait 7 cycles (350 ns), you still have 140 ns for the signal to get out of the FPGA, reach the MCU and meet it's setup requirement. But since you said you're using resistors to slow down the signal.. maybe it's so slow 140 ns aren't enough? b) For PI, you can try to be a bit more pessimistic on the min delay, using 7 or 8 ns instead of 10. Though, if it works at 500 kHz but not 20, it's unlikely to be a hold violation.
