How to constraint my design using TimeQuest?

Regarding wire delay.

For PCB wire delay, I typically use 4-8 ps/mm. For cables.. depends on the cable.

If I have it, I also tell TimeQuest the pin load capacitance, which it will use.

But that assumes the load is mostly capacitive, with negligible resistance.

Since you use Rs to slow down the slew, you have a RC load, which TimeQuest doesn't model.

Either you calculate the effect of your RC load.. or you just measure the rise time in your scope and add that to your I/O delay.

Regarding clock skew.

The clocks in the two chips (sender and receiver) are not 100% in phase, due to wire delay between them (and clock buffers if you have them).

If the sender's clock is a 5 ns ahead the receiver, then the receiver will get the data 5 ns earlier => subtract 5 ns to the delay

If the sender's clock is a 5 ns behind the receiver, then the receiver will get the data 5 ns later => add 5 ns to the delay

That said, the importance of precision in this estimates is relative.

As long as your design isn't suffering from being over constrained, you can use rough but safe estimates.

You're operating at low frequencies, you should have big timing margins.