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Honored Contributor
Honored ContributorHow to constraint my design using TimeQuest?
I am looking for some help to constrain my design. I've never done a timing constraint and my understanding of the subject isn't very deep at all. An overview of my design: it consists of a 72 ...
Altera_ForumHonored Contributor
Honored ContributorSetting I/O constrains is all about describing to TimeQuest what's going on outside the FPGA.
Since the MCU is probably using SCK to sample SO, then that would be the way to go, if you want to apply an output constraint. But then again, I'd take a very different approach to this problem. I'd run my SPI interface logic on SCK, constraining SCK as a clock and constraining nCS and SO in relation to SCK. In the way you're doing it, using sys_clk to run the SPI interface logic, the best way may be to set a false path in SO as well. Since your 20 MHz clock is way faster than the 2 MHz SCK, you should be able to generate a SO signal which meets the MCUs timing requirements easily. 10 ns tHold => make sure you wait at least 1 clock (of sys_clk) between the rising of SCK and changing SO. 10 ns tSetup => make sure you wait less than 9 clocks between the rising of SCK and changing SO.
