Honored Contributor
Honored ContributorThank you for taking out the time to reply. The Parallel-in Shift Out design has the following ports:
CLK, SO/MISO, SCK, CS, nRESET and PI[72] Regarding (2): The MCU is a AT Mega 1281 and the data sheet specifies only typical values for the SPI interface. It lists tSetup and tHold as 10 ns. How would I go about estimating wire delay and clock skew? Here's the table that lists the tSetup and tHold: http://i.imgur.com/KWPlG.png The MCU is the master and sets the SPI bus speed, which is yes 2 MHz. However, SCK is synchronized with the CPLD's 20 MHz clock. If I understand your suggestion correctly, you're saying that I should declare SCK to also be a clock in the SDC file and constrain SO in relation to that? Even though I'm not directly using SCK, I sync the signal via two flip-flops and detect the rising falling edges of the synced signal. I then shift out the data onto SO based on the falling edge of the synced SCK signal.
