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Honored Contributor
Honored ContributorHow to constraint my design using TimeQuest?
I am looking for some help to constrain my design. I've never done a timing constraint and my understanding of the subject isn't very deep at all. An overview of my design: it consists of a 72 ...
Altera_ForumHonored Contributor
Honored Contributor1) Doesn't your Parallel-in, Shift-Out design have more ports than those?
2) You should set a max output delay and a min output delay on SO. The max value will include the MCUs tSetup, while the min value will include the MCUs tHold. They should also include an estimate of wire delay and an estimate of clock to data skew. max output delay = tSetup + maxWireDelay + worseClockSkew min output delay = -Hold + minWireDelay - worseClockSkew And isn't your MCU capturing SO using the 2 MHz SCK? If so, you should constrain SCK and constraint SO in relation to SCK. 3) They look reasonable. But again max input delay = tCO + maxWireDelay + worseClockSkew min input delay = tCO_min + minWireDelay - worseClockSkew
