How to constraint my design using TimeQuest?

Thanks

Here's my SDC file for the Parallel In Shift Out design:

create_clock -name sys_clk -period 50 
set_false_path -from  -to 
set_false_path -from  -to 
set_false_path -from  -to 
set_input_delay -clock { sys_clk } -max 25 }]
set_input_delay -clock { sys_clk } -min 10 }]
set_output_delay -clock { sys_clk } 15 

I still have a couple of questions: I actually had the design working on a real board and I didn't really "bother" with the timings before this because the design worked at a low speed (500 KHz SPI bus with an 8 MHz oscillator. I was also unaware how critical they were.). However, I now have the deign working at 2 MHz (with a 20 MHz clock) and a seemingly random bug starts popping up:

As mentioned, I use SPI to transfer data from the CPLD back to the MCU (the CPLD can also be on a different board but is always connected via a short wire and also has a series resistance to slow down the rising/falling edges). Yesterday, when I had the board running without proper constraints, I had rather frequent incorrect data transfers. One in 20 data transfers would fail (I know they'd fail because I compare the data against a stored array of bytes in an EEPROM).

However, after some help from this thread and reading Altera's tutorial I set up the timings as shown in the above code. I reprogrammed all the CPLDs and the issue is MUCH MUCH less frequent but unfortunately still happens.

Before, one in 20 data transfers would be bad. Now, one in 10,000 are bad. My question is, could timings still be behind this? Because I set up the timings the first time I'm not sure I did it correctly. For instance, the 15 ns delay for SO in the above code was something I guessed at random. How do I properly determine this? The MCU details it's setup and hold timings for SPI as 10 ns (typical). Should the output delay for SO be less or more than this?

The min and max delays for PI[*] I got from my 'other design' which listed the max. clock to output delay as 19 ns and min. clock output delay as 9 ns. Are my values of 25 and 10 reasonable? I suppose my question really is that, basically, how do I find out what values to set for input and output delays?

If you folks feel that timings aren't behind this than perhaps I should shift to LVDS instead of relying on SPI to transfer data over a 5 inch ribbon cable. I would massively appreciate any advice on this.