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Altera_Forum's avatar
Altera_Forum
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13 years ago

How to constraint my design using TimeQuest?

I am looking for some help to constrain my design. I've never done a timing constraint and my understanding of the subject isn't very deep at all. An overview of my design: it consists of a 72 ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

The other FPGA's clock to output delay will becomes (part of) this FPGA's input delay.

So, you probably want something like

set_input_delay -clock SYSTEM_CLOCK -max 20 [get_ports my_inputs[*]]

set_input_delay -clock SYSTEM_CLOCK -min XX [get_ports my_inputs[*]]

You can get the XX value from the minimum clock to output delay report.

Translation: this would be telling TimeQuest that the signal will reach the FPGA pins XX to 20 ns after the rising edge of SYSTEM_CLOCK.