How to constraint my design using TimeQuest?

Ah yes, I'll definitely do that. As a further question, I've fixed almost all the timing constraints in my design except this:

DO <= out_reg(out_reg'high) when nCS = '0' else 'Z';

This is a combinational one and so I'm kind of confused. I think I use the set max delay and set min delay for these? If I set set max delay to 20 and set min delay to 5, I get a setup time violation and Im not sure why. But if I only specify the max delay, I get no violations but im told that DO is only partially constrained.

Another path that's unconstrained is out_reg[7] to DO. I assume that's also fixed by setting min/max delays?

All of this is so confusing and none of the books I've read cover timing constraints and even if I somehow fix something in the SDC file, I feel like I don't know what I'm doing!

EDIT: Using Set Output Delay fixed the issue! Now I only have to figure out how to tell TimeQuest that the 72 inputs will have a clock to output delay of 20 ns.