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So from now on, the entire design uses statements like
if nRESET_sync = '0' then
---do stuff
Right?
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Essentially.
However, its much easier to design your logic as components. In the top-level of the design you instantiate the reset synchronizer component and connect the synchronized output to the reset in your design. If you name your top-level reset differently than the reset port on your components, then you can do something like:
-- Synchronized reset
signal rstN : std_logic;
...
u1: sync
...
d => ext_rstN,
q => rstN
...
u2: mydesign
...
rstN => rstN,
...
Cheers,
Dave
Honored Contributor
