How to constraint my design using TimeQuest?

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Could you provide an example?

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Sure, you use the same component, with a slightly different connection:

sync1 : sync
        generic map(
            RESET_STATE => '0'
        )
        port map(
            clk  => clk,
            rstN => nRESET,
            d    => '1',
            q    => nRESET_sync
        );

So how does this work?

Well, when nRESET is low (active), the registers internal to this synchronizer are immediately cleared and output '0', i.e., the nRESET_sync signal is asynchronously asserted. When nRESET is high (deasserted), the synchronizer chain starts to synchronize the input d, which in this case is a '1'. After a couple of clocks, the '1' appears at the synchronizer output, and viola, the nRESET_sync signal deasserts synchronously.

Cheers,

Dave