How to constraint my design using TimeQuest?

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You should run reset through a reset synchronizer, i.e., a synchronizer that asserts reset asynchronously, but deasserts it synchronously, and then apply a false path. The reset and recovery time for the registers internal to the design will then be analyzed with respect to the synchronous deassertion of the reset signal.

Cheers,

Dave

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Could you provide an example? At the moment, I'm syncing signals like this:

sync1 : sync
		generic map(
			RESET_STATE => '0'
		)
		port map(
			clk  => clk,
			rstN => nRESET,
			d    => sck,
			q    => SCK_sync
		);

I also read up on your byteblaster example but I don't think that implements a reset synchronizer.