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why are we setting the synced signals as False Paths? Why do they not need a timing analysis?
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They are asynchronous signals, and you expect metastable states on those signals, right? That is why you have put a synchronizer on those signals. A timing analysis of those asynchronous inputs is meaningless, since the timing of a transition on the input is completely arbitrary with respect to the clock used by your FPGA logic. Once you have synchronized that signal, it is synchronized to the FPGA clock, and the FPGA clock constraint takes over.
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One more question, what do I do with RESET? Is that also a false path? The RESET goes to a lot input paths it seems.
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You should run reset through a reset synchronizer, i.e., a synchronizer that asserts reset asynchronously, but deasserts it synchronously, and then apply a false path. The reset and recovery time for the registers internal to the design will then be analyzed with respect to the synchronous deassertion of the reset signal.
Cheers,
Dave
Honored Contributor
