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1) I went and created a clock of time period 50 ns (20 Mhz) and assigned the port to CLK. I named this SYSTEM_CLOCK.
2) I then went to the Set Output Delay dialog box and entered a delay of 2 ns. I chose SYSTEM_CLOCK as the clock and chose my 72 outputs.
3) I went into the Contraints menu and chose "Set False Paths". In the FROM field I put in SYSTEM_CLOCK and in the TO field I put in SCK. I did this again for CS and MOSI. I don't think I did this step quite right because in the reports I'm still told that I have 4 unconstrained inputs. Where do I tell TimeQuest that these are False Paths?
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If you are creating new constraints, then you have to re-run the analysis.
Personally I create the .sdc file directly, and only use the GUI for analyzing the timing.
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5) I found the clock to output delay for my outputs. Do I just use these for my other design which has 72 inputs? Will 17.968 ~= 20 ns become the input delay?
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I forget whether you enter them directly, or indirectly via a calculated input delay, that is why I wrote the other tutorial. Read it. The answer should be in there :)
Cheers,
Dave
Honored Contributor
