Honored Contributor
Honored ContributorOK, I have an update.
Here is what I did, for the 'other FPGA', step by step (I did this so I could get an actual figure for the clock to output delay). The overall input/outputs are very similar to that of the design I described in my initial post except the CPLD has 72 outputs instead of inputs. It also has a fully functional SPI interface and a active-low RESET. I followed the TimeQuest Tutorial as I did this. 1) I went and created a clock of time period 50 ns (20 Mhz) and assigned the port to CLK. I named this SYSTEM_CLOCK. 2) I then went to the Set Output Delay dialog box and entered a delay of 2 ns. I chose SYSTEM_CLOCK as the clock and chose my 72 outputs. 3) I went into the Contraints menu and chose "Set False Paths". In the FROM field I put in SYSTEM_CLOCK and in the TO field I put in SCK. I did this again for CS and MOSI. I don't think I did this step quite right because in the reports I'm still told that I have 4 unconstrained inputs. Where do I tell TimeQuest that these are False Paths? http://i.imgur.com/ncyOp.png 4) I'm also told that MISO (which I call DO in the design) isn't constrained even though I did set an output delay for it. Infact, SDC Assignments/ Set Output Delay has it in the report as well. http://i.imgur.com/2eVq6.png 5) I found the clock to output delay for my outputs. Do I just use these for my other design which has 72 inputs? Will 17.968 ~= 20 ns become the input delay? http://i.imgur.com/GzPWk.png Thanks for taking the time to respond! Would have never gotten to where I am without your help!
