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Yes, SCK and CS are run through synchronizers but not MISO and MOSI. I'll set CS and SCK as false paths. I'll try what you suggested about MISO. Should I also sync MOSI? [actually, currently, I'm not even using MOSI but would like to know for future reference.]
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Since you know that MISO is only ever registered based on a synchronized version of SCK, you can also set that as a false path.
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Regarding the parallel input. The parallel input comes from another FPGA/CPLD. How can I find out the clock-to-output delay? Where do I tell TimeQuest about this?
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TimeQuest for the 'other FPGA' will tell you. Look at the 'datasheet' report. Bring up the TimeQuest GUI and you'll see that report listed. The PDF that I linked to above has plenty of examples of reading that information.
The clock-to-output delay from that report can also be used as your requested setting for the MOSI output, just set the requirement for the clock-to-output delay to be slightly larger than the largest value reported, and TimeQuest will be able to 'meet' that requirement. The clock-to-output delay can be adjusted slightly by Quartus by using the IOE output registers. Quartus has much more flexibility in adjusting the input delays, since there are programmable delay cells in FPGA IOE inputs.
Cheers,
Dave
Honored Contributor
