How to constraint my design using TimeQuest?

Hi Dave, was hoping you'd reply. :)

Yes, SCK and CS are run through synchronizers but not MISO and MOSI. I'll set CS and SCK as false paths. I'll try what you suggested about MISO. Should I also sync MOSI? [actually, currently, I'm not even using MOSI but would like to know for future reference.]

Regarding the parallel input. The parallel input comes from another FPGA/CPLD. How can I find out the clock-to-output delay? Where do I tell TimeQuest about this?

I already went through that thread and also your PDF. I've done followed through the TimeQuest Tutorial and that also was a big help.