Honored Contributor
Honored ContributorYou probably need the following constraints;
1) A clock frequency constraint for the FPGA clock. This constrains the register-to-register paths inside the FPGA. Quartus/TimeQuest use this constraint to check that your internal logic can operate at the frequency of the clock. 2) The SPI inputs are run through synchronizers correct? In that case, you can set them as false-paths. This tells TimeQuest; "These inputs do not need to be analyzed". 3) For the SPI outputs, you can give it a constraint "that the FPGA can meet". How do you know what it can meet? You put it to 10ns to start with, and then look at the report to see if it failed, and then increase it a little. 4) Where is your parallel input coming from? If you have an external device that is writing to the FPGA, then it will have a clock-to-output delay. Its that delay that you need to tell TimeQuest about, so that it can look at the timing at the FPGA input registers to see if the register setup and hold time can be met. There's a tutorial and references in this thread: http://www.alteraforum.com/forum/showthread.php?t=31457 Cheers, Dave
