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Altera_Forum's avatar
Altera_Forum
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17 years ago

How to constraining clocks in dcfifo

Hi,

I've got a dcfifo with read clock and write clock. The write clock is using the coreclkout from the alt2gxb and is clocking in the 64-bit data from the alt2gxb rx output bus into the fifo. The read clock is the same frequency as the write clock but a different phase and it takes the data from the fifo and sends to a lvds block. The fifo is set to run continously (rd/wr request is always active).

How do I constrain this correctly? I've tried using the 'set_clocks_groups' command but I don't know if I'm using it correctly. I've tried to put all the different clock domains in a different group. But happens if a clock is used in two different sections but the paths in those sections are completely independent?

Thanks

MT

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Starting with version 8.0, the dcfifo megafunction automatically produces set_false_path exceptions for TimeQuest similar to the cut-path settings it automatically creates for the Classic Timing Analyzer. You should be able to see these exceptions by running "Report SDC" in TimeQuest. In QII 8.0 and 8.1, you shouldn't need to do anything extra to cut cross-domain paths if all the cross-domain paths go through dcfifo.

  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Thanks for the info.

    You'er right in what you say but I haven't found it to work. The set false paths give warnings, when you re-run the design, saying that the paths can't be found.

    If I leave out some clock group constraints then it tries to constrain paths with ridiculous timing constraints. If you look at what it was trying to do, it's trying to constrain the pointers in the FIFO at with a timing constraint of 0.8ns! The clock is 6.4ns.

    So, something isn't working. Perhaps because the false paths aren't working, there is a knock on effect with everything else.
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    --- Quote Start ---

    The set false paths give warnings, when you re-run the design, saying that the paths can't be found.

    --- Quote End ---

    Even with the Classic Timing Analyzer you often get some of these automatic cut-path settings listed in the table of ignored settings. With TimeQuest in QII 8.0, I think I've seen different set_false_path exceptions being used from one FIFO to the next.

    I've never looked in detail at this, but I've always assumed that depending on the configuration of the dcfifo not all cut-path settings or set_false_path exceptions created by dcfifo apply. dcfifo will create the superset of all the ones that could be needed for any design.

    --- Quote Start ---

    If I leave out some clock group constraints then it tries to constrain paths with ridiculous timing constraints. If you look at what it was trying to do, it's trying to constrain the pointers in the FIFO at with a timing constraint of 0.8ns! The clock is 6.4ns.

    --- Quote End ---

    This does sound like the automatic set_false_path exceptions aren't working. If those 0.8 ns constraints are a setup relationship between the two FIFO clocks, then that was almost certainty for paths that you are allowed to cut. The 0.8 ns is probably the phase relationship between the two clocks.