how to constrain routing in cyclone fpga?

Incremental Compilation is where to start. You make partitions on hierarchies of the design, and can set them to post-fit so that if they don't change, they remain locked down. Most of the time you have to then floorplan with LogicLock, because the partitions are still placed all around each other, and so if you have to fit the changed partition within the holes of the locked down stuff, it becomes a much more difficult problem.

In q10.1, you might want to look at Assignments -> Settings -> Compilation -> Rapid Recompile. This is the "holy grail" in that it trys to figure out the changes you've made and only refit those, but I'm not sure how well it works.

In the end, everyone gets annoyed that other parts of the design must be refit even though their logic didn't technically change. It takes time, and it can make results bounce around(although good timing constraints would stop this from being a problem). This is how place-and-route works, and if there was an easy solution it would have come out during the past 20 years. (Again, rapid recompile has that as a goal, but I'm not sure how far along it is.)