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MOliv45's avatar
MOliv45
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1 year ago

How to constrain inter-clock transfers with very low default relationiship (1 ps)?

=== SHORT INTRO === Due to some questionable architecture decisions in the past, we ended up with a large circuit implemented in three related clock frequencies using timing division multiplexing. T...
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FvM's avatar
FvM
Icon for Super Contributor rankSuper Contributor
1 year ago

Hi,

you have 14 ns between launch and latch clock, ages for a simple register-to-register transfer.

I don't recognize at first sight how to constrain the transfer intelligently. In case of doubt specify asynchronous domains and a delay statement.

MOliv45's avatar
MOliv45
Icon for New Contributor rankNew Contributor
1 year ago

Hi @FvM,

Exactly, the slack is very large, but indeed I don't know yet the recommended way to constrain such path. Also it is confusing the default setup relationship being 1 ps.