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Honored Contributor
Honored ContributorHow to constrain a clock coming from HPS as input clock to FPGA?
Hi I am Using Cyclone V SoC 5CSXFC6C6U23I7. to build the system I have used HPS output clock for FPGA. so there is no clock PIN I have used in My design from FPGA side. Hence I am unable to ap...
Altera_ForumHonored Contributor
Honored ContributorAlso moving this post to the device discussion since more people will see it up there.
