How to connect one PCIe Reference clock to TWO GXB banks in Arial10?

For PCIe Gen3x8, you will be using 8 transceiver channels. However, you only need one PCIe reference clock. The reference clock will be connected to 1xATX PLL and 8 CDR of 8 receiver channels through internal clock networks (within FPGA). Quartus Prime will handle the internal clock connection. All user need to do is specify the Pin where the PCIe REFCLK is to be connected. Regards, Nathan