How to configure DDR3 and calculate parameters of DDR3 controller with uniphy?

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There will be a model, for the DDR3 part used on that development board, listed in the 'Presets' panel on the right hand side of the UniPHY settings window. Select the part used from that list and it will populate all the fields for you. The part used on the development board will be listed in the user guide that came with the board.

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thank your answer, but tratix V DSP Development Kit use MT41J128M16HA-125 DDR3 and MT41J128M8JP-125 DDR3 of Micron, they are not in list the "Presets", so I think I will configure and caculate board setting parameters include setup and hold derating, board skew. But I don't know how to do it now?

In the kit that came with the board are a number of options. If you don't have the kit you can download it from:

http://www.altera.com/products/devkits/altera/kit-stratix-v-dsp.html (http://www.altera.com/products/devkits/altera/kit-stratix-v-dsp.html)

Within that kit there is an 'SI document' that discusses specifics of the board implementation although, I admit, it doesn't appear to specify the board trace delays.

There is also a board file (s5_pcie_devkit_revc.brd) from which you could extract exact trace delays. However, you need an Allegro license which, perhaps, you don't have.

So, the best option is to open one of the design examples. In the 'examples' directory there is a 'ddr3x72' project in the 'memory' folder. Unzip it and open it in Quartus. Run Qsys and open 'ddr3_x72_qsys.qsys'. You can now explore the 'mem_if_ddr3_emif_0' component and all the settings Altera used for the memory Phy and board. This should provide you with the settings you need to get your project up and running.

Regards,

Alex

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In the kit that came with the board are a number of options. If you don't have the kit you can download it from:

http://www.altera.com/products/devkits/altera/kit-stratix-v-dsp.html (http://www.altera.com/products/devkits/altera/kit-stratix-v-dsp.html)

Within that kit there is an 'SI document' that discusses specifics of the board implementation although, I admit, it doesn't appear to specify the board trace delays.

There is also a board file (s5_pcie_devkit_revc.brd) from which you could extract exact trace delays. However, you need an Allegro license which, perhaps, you don't have.

So, the best option is to open one of the design examples. In the 'examples' directory there is a 'ddr3x72' project in the 'memory' folder. Unzip it and open it in Quartus. Run Qsys and open 'ddr3_x72_qsys.qsys'. You can now explore the 'mem_if_ddr3_emif_0' component and all the settings Altera used for the memory Phy and board. This should provide you with the settings you need to get your project up and running.

Regards,

Alex

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Thank your answer, I have refered the 'ddr3x72' project and configured the parameters as it. But I don't know why DDR3 still don't run. when I access in DDR3, the programming is suspended. if I remove the code write/read to/frome DDR3, the programming normal runs. I think, the DDR3 still have not been active yet.

Hi,

You should check the clock of your ddr3 controller,

Most of time the problem stems from the clock.

Check especially that you have connected the right oscillator for the ddr3 pll clock input.

regards,

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Hi,

You should check the clock of your ddr3 controller,

Most of time the problem stems from the clock.

Check especially that you have connected the right oscillator for the ddr3 pll clock input.

regards,

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Thank for your answer, I have solved the issue.