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In the kit that came with the board are a number of options. If you don't have the kit you can download it from:
http://www.altera.com/products/devkits/altera/kit-stratix-v-dsp.html (
http://www.altera.com/products/devkits/altera/kit-stratix-v-dsp.html)
Within that kit there is an 'SI document' that discusses specifics of the board implementation although, I admit, it doesn't appear to specify the board trace delays.
There is also a board file (s5_pcie_devkit_revc.brd) from which you could extract exact trace delays. However, you need an Allegro license which, perhaps, you don't have.
So, the best option is to open one of the design examples. In the 'examples' directory there is a 'ddr3x72' project in the 'memory' folder. Unzip it and open it in Quartus. Run Qsys and open 'ddr3_x72_qsys.qsys'. You can now explore the 'mem_if_ddr3_emif_0' component and all the settings Altera used for the memory Phy and board. This should provide you with the settings you need to get your project up and running.
Regards,
Alex
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Thank your answer, I have refered the 'ddr3x72' project and configured the parameters as it. But I don't know why DDR3 still don't run. when I access in DDR3, the programming is suspended. if I remove the code write/read to/frome DDR3, the programming normal runs. I think, the DDR3 still have not been active yet.
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