how to clear the ram content in one clock?

hi all,

I used RAM ip core or the RAM verilog code I written, and want to reset all the content of the memory to 0. I only find the way to write one zero at corresponding address of the RAM in one clock. So to clear a RAM with 1024 depth needs 1024 clocks, it cost too much time. Anybody has good method to clear it in one clock?

I even rewrote the ram using verilog code, if adding the clear function, it can't be synthesize to block RAM of the altera FPGA. What's the matter here?

this is the code:

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module dpram (

clk_i,

clear_i,

wen_i,

addrin_i,

d_i,

clkout_i,

addrout_i,

d_o

);

parameter DWIDTH = 16;

parameter AWIDTH = 16;

parameter DEPTH = 64;

input clk_i;

input clear_i;

input wen_i;

input[AWIDTH-1:0] addrin_i;

input[DWIDTH-1:0] d_i;

input clkout_i;

input[AWIDTH-1:0] addrout_i;

output[DWIDTH-1:0] d_o;

reg[DWIDTH-1:0] mem[DEPTH-1:0];

reg[AWIDTH-1:0] addrb_reg;

integer i;

//if remove clear function, the dpram can be synthesized to ram block

always @(posedge clk_i ) begin:clear

if (clear_i) begin

for(i=0; i<DEPTH; i = i+1)

mem[i] <= 0;

end

end

always @(posedge clk_i )

begin:wr

if (wen_i) mem[addrin_i] <= d_i;

end

always @(posedge clkout_i)

begin:rd

addrb_reg <= addrout_i;

end

assign d_o = mem[addrb_reg];

endmodule

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