How to check clocks using SignalTap II Logic Analyzer?

Hi all,

I am learning how to use Signaltap II logic analyzer using this tutorial:

http://www.altera.com/literature/hb/qts/qts_qii53009.pdf?gsa_pos=1&wt.oss_r=1&wt.oss=design%20debugging%20using%20the%20signaltap%20ii%20logic%20analyzer

Among many advantages of using this analyzer, my first basic concern is how to use the ELA to check/confirm the system clock of a design running in FPGA device? I want to make sure that the clock is fed properly.

PS: Actually, I have checked the clock using the JTAG_debug service with the commands jtag_debug_sample_clock and jtag_debug_sense_clock. But the result seems to be not consistent as sometimes clock is toggled and sometimes not. If someone can help explain how to use these commands to verify clock?

Any comment or suggestion is highly appreciated. Thanks in advance.