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Altera_Forum's avatar
Altera_Forum
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16 years ago

How to activate the "VCO Bypass Mode" of the Stratix IV PLLs ?

In a Stratix IV GX design, I'd like to place the Left and Right PLLs in vco bypass mode.

This mode is recommended in ALTERA documentation to avoid jitter amplification when you generate the transceiver clocks with the 6G ATX PLL whose input reference clock is provided by the Left or Right PLL cascade clock lines.

I haven't find any practical information, neither in documentation nor in the ALTPLL or ALTGX MegaWizard PlugIn manager steps, that permit me to bypass the VCO of the PLL !??

Does anyone how to proceed ?

Thanks.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    16 years ago

    Fixed it (at last !...).

    What a pity the solution is hiden in a "Configuration example" chapter of the device Handbook. It would be better placed in the "L/R PLL in VCO Bypass Mode" chapter

    For complete solution, see Stx IV Handbook p2-77 that describes the restrictions and the tricky way to proceed