How to activate the "VCO Bypass Mode" of the Stratix IV PLLs ?

In a Stratix IV GX design, I'd like to place the Left and Right PLLs in vco bypass mode.

This mode is recommended in ALTERA documentation to avoid jitter amplification when you generate the transceiver clocks with the 6G ATX PLL whose input reference clock is provided by the Left or Right PLL cascade clock lines.

I haven't find any practical information, neither in documentation nor in the ALTPLL or ALTGX MegaWizard PlugIn manager steps, that permit me to bypass the VCO of the PLL !??

Does anyone how to proceed ?

Thanks.