How to Achieve Independent Control of LUT Outputs in Agilex 5 FPGAs?

On older chips, the delay really does ripple down the chain. However, on the Agilex 5, if you implement it in silicon, you'll notice that it starts bouncing ahead by cells, then half labs, and then full labs due to its built-in carry lookahead type circuitry. As a result, you won't see uniform delay steps on the sum outputs.

To achieve the desired pattern and performance, we recommend experimenting with hardware configurations to find the best fit for your needs. One effective approach is to switch from using carry chains to wire LUTs. For example:

VERILOG

wire [19:0] delay_line /* synthesis keep */;

assign delay_line = {delay_line[18:0], din};

wire dout = delay_line[19];

You can easily place this configuration using location assignments by dragging and dropping in the Chip Planner, allowing you to create any layout you prefer. Once you have a layout that works for you, you can then in mass-producing it.