how the data is transfered using PCIE LINK

so after some research, i find out:

assume there is only one RC, and one EP device...so the BAR address range is basically one to one mapped on the End point device, right?

so, does that mean, if my end point device needs 4G address range, then the BAR will be 4G big?

Next question, when i use PCIE compiler, the BAR0 and BAR1 is together formed a 64bit memory space, what does this mean? for me, it looks like a 32 bit memory address but with size as the sum of BAR0 and BAR1

Last question, i am using the descriptor packet in side fpga, and the databus is 64 bit wide, so my question is:

at the RC side/PC, how many bytes of data does each BAR address points to? 1 byte?

if its 1 byte, and i want to transfer 2k byte to the end point device, so i just write 2k BAR memory space?

Do I need to trigger the sending action? or once the max_payload is formed, the packet will be sent automatically?

Appreciated.