Forum Discussion
2 Replies
- Altera_Forum
Honored Contributor
Since you have the code written in VHDL you have only to write a testbench file related to your module.Try to make a project in ModelSim containing both the module and the testbench.
- Altera_Forum
Honored Contributor
Hi Emilio, recently I learned how I can debug avalon bus signals.
Follow this guide : ftp://ftp.altera.com/up/pub/tutorials/de2/digital_logic/tut_signaltapii_vhdlde2.pdf you can also acces to this document and other following this link http://www.altera.com/education/univ/materials/manual/unv-lab-manual.html. Use Signal TAP II, compile your project and download sof file on yor board, then run NIOS2 EDS using debug perspective, in this way you can follow AVALON BUS Signals step by step.