Forum Discussion
Altera_Forum
Honored Contributor
16 years agoSince you have the code written in VHDL you have only to write a testbench file related to your module.Try to make a project in ModelSim containing both the module and the testbench.
Since you have the code written in VHDL you have only to write a testbench file related to your module.Try to make a project in ModelSim containing both the module and the testbench.