Forum Discussion
New ContributorHow long should rx_is_lockedtodata be asserted before a valid connection can ACTUALLY be assumed?
Hi,
If during the toggling, the rx_is_lockedtodata assertion duration is longer than 4us, you can try to workaround by monitoring the RX signal detect to ensure valid signal presence before you check on the CDR status. Note that you would need to enable 8b10b block to use RX signal detect. You will need to set the signal detect thresholds according to your specific setup. You may refer to the SATA/SAS recommended QSF assignments in the V series XCVR PHY IP user guide -> Cyclone V Transceiver Native PHY IP Core -> "Enable rx_std_signaldetect port" section for further details.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
Regular ContributorHi,
If during the toggling, the rx_is_lockedtodata assertion duration is longer than 4us, you can try to workaround by monitoring the RX signal detect to ensure valid signal presence before you check on the CDR status. Note that you would need to enable 8b10b block to use RX signal detect. You will need to set the signal detect thresholds according to your specific setup. You may refer to the SATA/SAS recommended QSF assignments in the V series XCVR PHY IP user guide -> Cyclone V Transceiver Native PHY IP Core -> "Enable rx_std_signaldetect port" section for further details.
Please let me know if there is any concern. Thank you.
Best regards,
Chee Pin
New ContributorHad to tweak XCVR_RX_SD_THRESHOLD and XCVR_RX_COMMON_MODE_VOLTAGE values to 3 and VTT_0P70V respectively to get things working for PCML-1.5, but that did the trick.
In fact, activating the signal detect circuit gates rx_is_lockedtodata as well, so the only change needed in my state machine was to remove the delay timer.
Is signaldetect just looking for the common mode voltage to be above the specified value or is it actually watching for transitions?
