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Altera_Forum
Honored Contributor
Honored ContributorHow long does the FPGA complete the initialization?
Hi dears: I found below information inside Altera configuration handbook: "By default, the internal oscillator is the clock source for initialization. If the internal oscillator ...
Altera_ForumHonored Contributor
Honored ContributorThanks for ur information!
Another question, the FPGA how to know which word or byte is the last one when configuring thru AS mode? Is there any sign inside configuration stream? If so, can user recognize it?
