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Altera_Forum
Honored Contributor
12 years agohi,
I used Avalon MM Slave template, I put the file in QSYS slave_template.v and I connected it to NIOS This template offers 16 registers I can read write data from register with the operations of IORD_32DIRECT (), IOWR_32Direct (). Now the problem is how do I create a component verilog / vhdl who make some operations with the values ​​loaded into the registers? in the file .v I've seen that the following signals are available: user_dataout_X user_datain_X how can I use them? can you give me a link to some examples?