how does quartus decide to remove logic?

I guess this is a bit of a newbie question (newbie to quartus not hardware design - I'm an old ASIC guy)...

I've crawled through the manual (well, it's 1200 pages long, so I'm sure I missed the discussion), but how does quartus decide to remove logic from a design? I have a big design (1.5M gates, 200K ff), and after mapping, 99% of the logic completely disappears and I am left with a few thousand luts.

I found the redundant logic options, noprune (which I am trying now with assorted regs, but so far by putting noprune everywhere except in tasks and functions, I get a hard crash:

Internal Error: Sub-system: VRFX, File: /quartus/synth/vrfx/verific/database/netlist.cpp, Line: 4538

What's confusing especially is that I think I've been careful to make sure data flows in and out of this design.. It simulates by driving data in from outside the chip only (though there may be an initial block somewhere?)

I presume that the problem is one of the follow:

1. map doesn't see clocks driven from registers (yes I read about clock generation), so it thinks all clocks a nailed to 0 or whatever...

2. map doesn't see that reset causes powerup fsms to start running..

3. ??? registers coming up 0 puts everything in a strange state and quartus removes logic thinking it won't start running..

I guess any of the above are fine, but *there's no clue* I can find in the reports or in the quartus that tells me *why* it tossed out all 200,000+ registers ? I suspect that design assistant might, but I haven't quite figured that out either?

Any hints much appreciated!