how does quartus decide to remove logic?

I remember pulling my hair out many moons ago when initially trying to keep logic on FPGA's. You will find that if you provide input into a module and have it drive another module that ultimately hooks to an output pin that your logic will stay in place (albeit sometimes optimized). On occassion, especially with cominatorial logic you will see your logic get squished. It may seem like overkill but if you are using VHDL it is very handy to label things. You can even label if and case statements and it will make things much easier to search for in RTL diagrams and when looking for signal nodes. Maybe you can do something similar in Verilog. 99.99% chance if you are missing modules in the final synthesized or mapped design, somewhere along the data path it didn't make it to an output pin or drive logic, and it's because you didn't hook up a signal properly to an input or output somewhere along the way.