Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

How do I synchronize gray code counts safely across asynchronous clock domains?

I have a design for a generic asynchronous FIFO that I have used for many years. In this FIFO, I use gray code counters for the read and write pointers to the core memory. These multi-bit pointers mu...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

I tried the multicycle with 2/1 and 1/0. In the latter case, I am now getting setup time violations, as well as the skew violation. The fitter is still inserting unnecessary (from my view) delay between flops. These flops are in the same or adjacent LABs, but the physical routing is going all over the place.

Is there a way in the sdc to do something like: "for each inst in { find ajbg_fifo } do { set_max_skew { -from {$inst.rdptr_rck} -to {$inst.rdptr_wck_s1} }"