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songsong96's avatar
songsong96
Icon for New Contributor rankNew Contributor
3 years ago

How do I select an FPGA chip with a high-speed system clock available?

Our team wants to implement an FPGA system that controls DAC Resolution 1ns width. The FPGA now in use is using Cyclone V (5ceba2f23c7). The 40MHz crystal clock is received from the outside, multipl...
FakhrulA_altera's avatar
FakhrulA_altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi songsong96,


Good day. For your question number 1 & 2, please refer to the following Datasheet on page 46 for High-Speed I/O Specifications, and page 40 for the PLL Specifications:


Cyclone V Device Datasheet


As regards restricted fmax, you cannot ignore the restricted fmax, it is the restricted performance that can be done based on your design. If you had a register in the DSP block, the restricted fmax will depend on the DSP block. If you assert a higher frequencies towards the restricted fmax, it will end up in violation within the DSP block to the output register.


This seems a device limitation, perhaps you may have to use a better performance device. Refer to the related link below:

Why does the TimeQuest timing analyzer report restricted Fmax with the reason "Limit due to hold check"?


Hope this can help.


Thank you.


Regards,

Fakhrul