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Honored Contributorhow do I generate 32k clock from cyclone V pll
Hi,
How do I use altera pll to generate 32k frequency in cyclone V? I need help for this one. Thanks18 Replies
Altera_ForumMinimum VCO frequency is 600MHz, so multiply by 4 is too little.
- Altera_Forum
The device handbook describes the limits for the PLL constants. You must stay within those limits. I suspect 250 is too large a divisor.
- Altera_Forum--- Quote Start --- Use the 'counter out to out cascade mode' of the Cyclone V PLL. For a 50MHz ref clock input (for example), use a multiply by 4 and divide by 25 to generate an 8.0MHz clock on pll_output_0. Then use pll_output_0 to pll_output_1 cascade mode with a division factor of 250 to generate 32.0KHz ( = 8.0MHz / 250 ) on pll_output_1. --- Quote End --- Hi, If I did this way, I got some error message like "the specified configuration causes VCO to go beyond the limit", and don't allow me to click finish button. what happen? Thanks, Jeff
- Altera_Forum
Use the 'counter out to out cascade mode' of the Cyclone V PLL.
For a 50MHz ref clock input (for example), use a multiply by 4 and divide by 25 to generate an 8.0MHz clock on pll_output_0. Then use pll_output_0 to pll_output_1 cascade mode with a division factor of 250 to generate 32.0KHz ( = 8.0MHz / 250 ) on pll_output_1. - Altera_Forum--- Quote Start --- The IP catalog has a module for a PLL generated clock. It will calculate the parameters needed to get your desired frequency or the closest available. --- Quote End --- Hi, Thanks, but it seems to me that it is impossible to get 32K from altera PLL directly. -Jeff
- Altera_Forum
The IP catalog has a module for a PLL generated clock. It will calculate the parameters needed to get your desired frequency or the closest available.
- Altera_Forum--- Quote Start --- Have you read this? www.altera.com/literature/ug/altera_pll.pdf?gsa_pos=2&wt.oss_r=1&wt.oss=altera_pll (http://www.altera.com/literature/ug/altera_pll.pdf?gsa_pos=2&wt.oss_r=1&wt.oss=altera_pll) From the Cyclone V handbook:
For Cyclone V, each of M,N,C can be 1..512. So if your input clock is 50MHz (as an example), then with M=2, N=125, C=25 will give an Fout of 32KHz (ie, 50e6*2/(125*25)). --- Quote End --- Hi, The PLL output frequency only gives me lowest value to 1.1718Mhz, and can't go lower than that. Is there any other way to let me generate 32k from altera PLL? Thanks, JeffEach Cyclone V PLL provides clock synthesis for PLL output ports using the M/(N × C) scaling factors. The input clock is divided by a pre-scale factor, N, and is then multiplied by the M feedback factor. The control loop drives the VCO to match fin × (M/N). - Altera_Forum
Have you read this? www.altera.com/literature/ug/altera_pll.pdf?gsa_pos=2&wt.oss_r=1&wt.oss=altera_pll (http://www.altera.com/literature/ug/altera_pll.pdf?gsa_pos=2&wt.oss_r=1&wt.oss=altera_pll)
From the Cyclone V handbook:
For Cyclone V, each of M,N,C can be 1..512. So if your input clock is 50MHz (as an example), then with M=2, N=125, C=25 will give an Fout of 32KHz (ie, 50e6*2/(125*25)).Each Cyclone V PLL provides clock synthesis for PLL output ports using the M/(N × C) scaling factors. The input clock is divided by a pre-scale factor, N, and is then multiplied by the M feedback factor. The control loop drives the VCO to match fin × (M/N).
