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Honored Contributor
9 years agoUse the 'counter out to out cascade mode' of the Cyclone V PLL.
For a 50MHz ref clock input (for example), use a multiply by 4 and divide by 25 to generate an 8.0MHz clock on pll_output_0. Then use pll_output_0 to pll_output_1 cascade mode with a division factor of 250 to generate 32.0KHz ( = 8.0MHz / 250 ) on pll_output_1.