how do I generate 32k clock from cyclone V pll

Use the 'counter out to out cascade mode' of the Cyclone V PLL.

For a 50MHz ref clock input (for example), use a multiply by 4 and divide by 25 to generate an 8.0MHz clock on pll_output_0.

Then use pll_output_0 to pll_output_1 cascade mode with a division factor of 250 to generate 32.0KHz ( = 8.0MHz / 250 ) on pll_output_1.