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Altera_Forum
Honored Contributor
16 years ago --- Quote Start --- Hi, do you have problems to achieve your required clock speed ? Are you shift registers as register implemented ? Kind regards GPK --- Quote End --- Yes, My registers are defined as you mentioned above, like this. reg [0:7] my_ram[0:63] I don't have a trouble of speed, my current solution works fine but it would be fine it it could work faster.