How can I set the DFE (Decision Feedback Equalization) in Adaptive Mode for the 10G transceivers inside Cyclone 10 GX?

HI Bogdan,

I verified using Quartus v18.0. Looks like Quartus v18.0 NativePHY IP IP doesn't support DFE setting as well. Only CTLE setting is shown in attached screenshot pic.

In short, the only escapee loophole is on ttk and Quartus assignment editor setting while NativePHY IP had mask off DFE setting. Cyclone 10 GX user guide also never mentioned about DFE support.

I have checked internally within Intel.

• Basically Cyclone 10 GX DFE is a hidden feature reserved for future use but as of now there is NO official support plan from Intel
• I am sorry but my answer to your question - "can we really count that these taps are really set?" is I am not sure as it's not tested feature in Cyclone 10 GX.
• Intel marketing decided to remove the support for DFE feature due to it's consuming more power and it's not meant to be used for lower end FPGA like Cyclone 10 GX. DFE is supported for mid range FPGA like Arria 10 and also on high end FPGA like Stratix 10.

I apologize for the confusion caused on ttk and Quartus assignment editor setting

BUT my advice to you is to not use DFE on Cyclone 10 GX as I can't guarantee whether it will work or not. I also don't have DFE register address mapping table to share with you as it's not supported feature yet.

Your understanding is highly appreciated here.

Thanks.

Regards,

dlim